The present invention relates to a semiconductor integrated circuit technique for addressing increase in speed of external output operation synchronized with a clock signal. More particularly, the invention relates to, for example, a semiconductor integrated circuit using, in an external interface portion, a MOS transistor having a breakdown voltage higher than that of an internal circuit and, further, to a technique effective to be applied to a burn-in method of such a semiconductor integrated circuit.
Japanese Unexamined Patent Application No. 9(1996)-8632 discloses a technique of stepping down an external power supply voltage within an LSI and making an external interface circuit operate with an external power supply voltage by using the stepped-down voltage as an operation power source of an internal circuit from a viewpoint of reduction in the size of a circuit device, reduction in power consumption, and the like. Japanese Unexamined Patent Application No. 2000-353947 discloses a technique in a semiconductor output circuit having a function of shifting the level of an internal signal to a signal level of a breakdown voltage of a semiconductor device or higher and outputting the resultant, and a function of outputting a signal at the internal signal level which is before the level shifting. In the semiconductor output circuit, for an output buffer in which a MOS transistor for protection used to increase a breakdown voltage between the gate and source of an output buffer transistor is provided on the power supply side, in order to prevent delay in speed of change in rising of a signal caused by on-state resistance of the MOS transistor for protection (the power supply voltage of the output buffer is the same as that in the internal circuit), the on-state resistance of the MOS transistor for protection is set to be varied by controlling a gate voltage.
In the conventional techniques, however, attention is not paid to delay in the output operation due to the level shifting function and, further, delay in external output operation due to propagation delay in a clock signal with respect to the point of addressing increase in the speed of external output operation synchronized with a clock signal. The inventor herein has examined the following points with respect to the point of addressing increase in speed of the external output operation synchronized with a clock signal.
First, the output operation delay due to the level shifting function was examined. For example, a semiconductor integrated circuit after a 0.35 xcexcm process internally uses an MOS transistor having a low breakdown voltage and uses a MOS transistor of a high breakdown voltage in an interface portion with the outside. To operate an internal circuit with a low voltage such as 3.3V and operate the interface portion with a high voltage like 5.0V, a level shift circuit for shifting a low-voltage amplitude to a high-voltage amplitude is inserted between the internal circuit and an input/output buffer. If a low-voltage power is supplied to both of the internal circuit and the interface portion, the whole semiconductor integrated circuit can operate with a low voltage. The inventor herein has therefore examined to mount a host interface module for an LPC (Low Pin Count) bus interface as a parallel interface in a PC (Personal Computer) (hereinbelow, also simply called an LPC module) on such a semiconductor integrated circuit. In a high-speed host interface specification such as the LPC, bus wiring is suppressed and, in addition, data communication is performed synchronously with a PCI (Peripheral Component Interconnect) clock of 33 MHz (external clock signal). Consequently, designing which is tighter with respect to signal propagation delay in a semiconductor integrated circuit is demanded. Regarding an external power supply as well, a small signal amplitude is realized by using a low-voltage power supply of 3.3V or the like. However, the inventor herein has found that delay in a data output timing from an external clock signal is increased by the output operation delay due to the level shift circuit and the propagation delay of the internal clock.
The inventor herein has consequently examined, against the output operation delay due to the level shift circuit, a countermeasure of bypassing the level shift circuit by master slice of a wiring layer since both of the internal circuit and the interface portion operate with only a low voltage in the case of assuring the operation of the LPC module. However, when the interface portion is operated with a high voltage such as 7.0V and the internal circuit is operated with a low voltage such as 4.6V in order to apply a high voltage to the MOS transistor having a high breakdown voltage at the time of burn-in, the level shifting function is not realized in the bypassed portion. Therefore, an intermediate potential is applied to a circuit like an inverter or clocked inverter which receives a small-amplitude signal and a shoot-through current flows in the interface portion. The shoot-through current causes shifting of a threshold voltage of a MOS transistor by hot carriers and destruction of a MOS transistor.
When a low voltage of about 4.6V is applied to both of the internal circuit and the interface portion at the time of burn-in, the problem does not occur. However, a sufficient voltage stress cannot be put on a MOS transistor having a high breakdown voltage, so that an initial failure cannot be found, and the possibility that the failure becomes apparent in the market after shipment becomes high. It is therefore unavoidable that reliability deteriorates. An external terminal for an LPC module is conformed with a PCI bus and is used in an environment where there is no termination using a reflection wave. In the worst case, a voltage twice as high as the power supply voltage is applied to the terminal. Consequently, the MOS transistor in the interface portion to be connected to the terminal is requested to have a high breakdown voltage.
Second, the external output operation delay due to the propagation delay of the clock signal was examined. For example, in an LPC module, output data has to be determined within predetermined permissible delay time since a rising change of a PCI clock of 33 MHz (external clock signal). It was found out by the inventor herein that, when the permissible delay time is shortened, if a clock signal generated by an internal CPG (Clock Pulse Generator) is used as a latch clock signal for data output, the output data may not be determined within the time.
An object of the present invention is to provide a semiconductor integrated circuit capable of realizing higher-speed external output operation synchronized with a clock signal from the viewpoints of prevention of the output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer.
Another object of the invention is to provide a semiconductor integrated circuit capable of realizing higher-speed external output operation synchronized with an external clock signal from the viewpoint of suppression of clock delay.
Further another object of the invention is to provide a burn-in method capable of improving reliability of burn-in in a semiconductor integrated circuit with higher speed of an external output operation synchronized with a clock from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the appended drawings.
The outline of representative ones of inventions disclosed in the specification will be briefly described as follows.
(1) A semiconductor integrated circuit of the invention achieved from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer includes a first circuit (4, 7) and a second circuit (3) having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other. The second circuit has: a plurality of level shift circuits (34, 35, 54, 55) capable of shifting the level of an output of the first circuit in accordance with an operation voltage of the second circuit; a plurality of external output buffers (33, 53) receiving outputs of the level shift circuits; a bypass (70, 71) for bypassing an input of a predetermined level shift circuit (54, 55) to an input of a predetermined external output buffer (53); and a selecting circuit (74) for selecting connection of either the predetermined level shift circuit or a bypass to an input of the predetermined external output buffer.
In a use form in which the first and second circuits operate with a low voltage, the bypass in the predetermined level shift circuit is connected to the input of the predetermined external output buffer. An external interface using the external output buffer connected to the bypass is not influenced by the operation delay by level shifting. Thus, a high-speed interface with the outside can be realized.
In a use form using a high voltage for an external interface as a request on a system to which the semiconductor integrated circuit is applied, the first circuit is operated with a low voltage, the second circuit is operated with a high voltage, a level shift circuit is interposed without selecting a bypass also in the predetermined external output buffer, the signal amplitude of a low voltage in the first circuit is shifted to the signal amplitude of a high voltage of the second circuit, and the resultant signal is supplied to the external output buffer.
Also in the case of employing any of the use forms, at the time of burn-in, the first circuit is operated with a low voltage for burn-in, the second circuit is operated with a high voltage for burn-in, a bypass is not selected in the predetermined external output buffer but the level shift circuit is interposed, the signal amplitude of the low voltage for burn-in in the first circuit is shifted to that of the high voltage for burn-in of the second circuit, and the resultant is supplied to the external output buffer. Since a shoot-through current does not pass to the second circuit by an intermediate-level signal having a relatively small amplitude of the first circuit, deterioration in the characteristic or destruction of the second circuit caused by the shoot-through current does not occur. Therefore, burn-in can be carried out in the first and second circuits by using the operation powers adapted to the breakdown voltages of the circuits, so that reliability of burn-in can be guaranteed.
(2) The level shift circuit may be constructed by a plurality of level shift circuits having level shifting ranges which are different from each other. When the operation voltages of the first and second circuits are different from each other, to deal with a case where the difference between the operation voltages is large, it is sufficient to prepare a plurality of level shift circuits which are optimum to level shift ranges and select a level shift circuit to be used in accordance with an operation voltage difference at the time of actually operating a semiconductor integrated circuit.
(3) As a concrete form of the invention, when the semiconductor integrated circuit has an internal power step-down circuit for stepping down an input voltage from a first external terminal (VCC), the second circuit uses an input voltage supplied to the first external terminal as an operation voltage. The first circuit uses, as an operation power, a stepped-down output voltage of the internal power step-down circuit or an input voltage from a second external terminal (VCL).
When the operation voltage of the first circuit and that of the second circuit are made different from each other, an external power supply voltage is connected to a first terminal and a stabilized capacitative element is connected to a second terminal. When the operation voltage of the first circuit and that of the second circuit are made equal to each other, the same external power supply voltage is connected to the first and second terminals. At this time, the operation of the internal power step-down circuit may be stopped. Since power supply capability is low as compared with the external power supply circuit, even if the internal power step-down circuit operates, there is no harm.
The first circuit may have register means (94) for holding selection control information (87) of the selecting circuit.
The first circuit has, for example, an output latch circuit (90) for latching output data of the predetermined external output buffer synchronously with a clock signal (104, 105) and a data processing circuit (20) for processing data to be latched by the output latch circuit.
The output latch circuit may be a part of a predetermined IO port or a dedicated circuit neighboring to the predetermined external output buffer. By disposing the output latch circuit adjacent to the external output buffer, propagation delay of latch data to the external output buffer can be reduced.
The clock signals may be supplied from the outside in parallel to the output latch circuit and the data processing circuit. When the output latch circuit receives a clock signal from the outside and performs the output latching operation, an influence of the clock delay in the output operation synchronized with the external clock signal can be reduced.
As a further concrete form, the data processing circuit is a host interface control circuit. For example, the host interface control circuit and the output latch circuit operate synchronously with the external clock signal of 33 MHz.
(4) In a burn-in method according to the invention of performing burn-in in a semiconductor integrated circuit including a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, in which operation voltages of the first and second circuits can be made equal to each other or different from each other, and the second circuit includes a level shift circuit capable of shifting the level of an output of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer receiving an output of the level shift circuit, and a bypass for selectively bypassing an input of a predetermined level shift circuit to an input of the external output buffer, operation voltages of the first and second circuits are made different from each other and no bypass selection is set in the bypass.
(5) A semiconductor integrated circuit according to the invention achieved from the viewpoint of suppression of clock delay has an external output buffer (53), a latch circuit (90) for latching data to be output from the external output buffer synchronously with an external clock signal (100), and a circuit (20) for processing data to be latched by the latch circuit. The latch circuit and the processing circuit commonly receive an output of a clock buffer (101) receiving the external clock signal.
The latch circuit receives a clock signal from the outside and performs an output latch operation, thereby enabling an influence of the internal clock delay in output operation synchronized with an external clock signal to be reduced.
When the latch circuit is disposed close to the external output buffer, the propagation delay of latch data to the external output buffer can be reduced.
It is also possible to provide an IO port (93) capable of latching data to be output from the external output buffer synchronously with an internal clock signal and selectively switch operation of the IO port and operation of the latch circuit.
(6) A semiconductor integrated circuit achieved from further another viewpoint of the invention has: a central processing unit; a clock generating circuit receiving a reference clock and generating an operation clock to be supplied to the central processing unit; an internal bus coupled to the central processing unit; a host interface module coupled to the internal bus, having a plurality of output buffers, a plurality of latch circuits for latching data to be output from the plurality of output buffers synchronously with an external clock signal, and a processing circuit for processing data to be latched by the plurality of latch circuits; and an external terminal to which the external clock signal is supplied from the outside. The plurality of latch circuits are disposed near the plurality of output buffers, and the external clock signal supplied to the external terminal is commonly input to the plurality of latch circuits.
As a concrete mode, the host interface module may be a host interface module for an LPC (Low Pin Count) bus interface.
As another concrete mode, the semiconductor integrated circuit may have an IO port capable of latching data to be output from the plurality of output buffers synchronously with an internal clock signal which is output from the clock generating circuit, and operation of the IO port and operation of the latch circuit can be selectively switched.
Further, the semiconductor integrated circuit may have an AD converter coupled to the internal bus, for converting an analog signal supplied from the outside to a digital signal, and the host interface module may supply the digital signal converted by the A/D converter to a host processor to be coupled to the semiconductor integrated circuit.